Field of the Invention
The present invention relates to a solid-state imaging apparatus and an imaging system.
Description of the Related Art
In an MOS type solid-state imaging apparatus, when very strong light such as a sun enters an angle of view of an imaging plane, there is a case where a phenomenon called a high luminance darkening (or, simply referred to as “darkening”) in which a center portion of the strong light is displayed in black occurs. Such a darkening occurs in the case of performing a CDS (correlated double sampling) operation for eliminating fixed pattern noises caused by a variation in threshold value of a transistor of every pixel or KT/C noises at the time of resetting. In the CDS operation, an N signal showing a noise level of the pixel and an S signal showing a data level are read out and a difference between the two signals is operated and output.
According to the Official Gazette of Japanese Patent Application Laid-Open No. 2008-42679, a difference between an S signal and an N signal is assured by a transistor for limiting the N signal on a pixel output line and limiting a level adapted to write the N signal into a holding capacitor for holding the N signal obtained after it was amplified by an amplifier unit, thereby preventing the darkening.
When the N signal is read out, if the strong light is irradiated to a photoelectric conversion unit, charges generated in the photoelectric conversion unit enter a floating diffusion region, thereby causing the N signal to be fluctuated from a correct level. When such a fluctuation is large, the difference between the S signal and the N signal is small, so that the darkening phenomenon occurs. In order to perform the CDS operation, symmetry between a circuit for holding the N signal and a circuit for holding the S signal is important.
However, according to the Official Gazette of Japanese Patent Application Laid-Open No. 2008-42679, since the N signal holding circuit and the S signal holding circuit have different configurations, there is a case where an elimination accuracy of the CDS deteriorates in dependence on values of the signals. Also in a method of limiting the N signal by changing a high level voltage of a control electrode of the transistor without using the transistor for limiting the level for writing the signal into the holding capacitor, voltage amplitudes of control electrodes of the two transistors differ. There is, consequently, a problem that the elimination accuracy of the CDS deteriorates due to a difference of charge injection or the like.